MANTIK DEVRELERİ LABORATUVARI DENEY FÖYÜ

EGE ÜNİVERSİTESİ MÜHENDİSLİK FAKÜLTESİ ELEKTRİK-ELEKTRONİK MÜHENDİSLİĞİ BÖLÜMÜ MANTIK DEVRELERİ LABORATUVARI DENEY FÖYÜ HAZIRLAYAN: Yard. Doç. Dr. Özkan AKIN ozkan.akin@ege.edu.tr 2017

İÇİNDEKİLER GENEL BİLGİLER ve UYARILAR... 3 DENEYLER YAPILIRKEN DİKKAT EDİLMESİ GEREKEN NOKTALAR... 4 RAPOR YAZIM KILAVUZU... 5 DENEYLER LAB #1: EXPERIMENT SET... 8 LAB #2: LOGIC GATES... 9 LAB #3: BASIC LOGIC FUNCTION... 10 LAB #4: NAND, NOR IMPLEMENTATION EXPERIMENTS... 11 LAB #5: ITERATIVE 2-BIT SUBTRACTER... 12 LAB #6: USING DATA SELECTORS 4-BIT ADDER... 13 LAB #7: FLIP-FLOPS AND ASYNCHRONOUS COUNTERS... 15 LAB #8:UP/DOWN COUNTER... 17 LAB #9: REGISTER DESIGN... 18 LAB #10: SHIFT REGISTERS... 19 EKLER Equipments List... 7 GUIDE TO ASSEMBLING YOUR CIRCUITS... 20 Digital TIPS: TTL vs CMOS... 26 The 555 Timer IC... 28

GENEL BİLGİLER ve UYARILAR Laboratuar çalışmalarının verimli olabilmesi için deneylerin aşağıdaki kurallara uygun olarak yapılması gerekmektedir. E.Ü. Eğitim-Öğretim Yönetmeliği, Madde 16: Uygulamalı veya uygulamadan oluşan derslerde uygulamaların % 80 ine katılmak ve başarılı olmak şarttır Laboratuvar uygulamasından başarısız olan öğrenciler dersten de başarısız sayılır. Deney grupları dönem başında belirlenecek ve dönem sonuna kadar değiştirilmeyecektir. Deneylerde kullanılacak malzemeler deney föylerinde belirtilmektedir. Laboratuvara gelmeden önce bu malzemeleri temin ediniz. Laboratuvara gelmeden önce ön çalışmada istenenleri mutlaka yapınız. Ön çalışma yapmayan grubun deney yapmasına izin verilmeyecektir. Deneyde yapılacaklardan herhangi biri bittiğinde görevliye gösterip onaylamasını isteyiniz. Deneye 15 dk. dan fazla geç kalan öğrenciler laboratuvara alınmaz. Öğrencinin gelmediği deneyden alacağı not sıfırdır. Öğrencinin yalnızca bir deneyi telafi etme hakkı vardır. Ders süresince laboratuardan çıkmak yasaktır. Gerektiğinde görevliden izin isteyerek çıkabilirsiniz. Deneylerini erken bitiren gruplar ders sona ermeden önce çıkabilirler. Deneyde kullanılacak olan ekipmanlar (el aletleri, kablolar, deney kitleri, ölçü cihazlarının tamamı) görevliden sayılarak teslim alınacaktır. Deney sonunda aynı malzemeler eksiksiz olarak geri verilecektir. Gruplar, kaybettikleri veya zarar verdikleri malzemenin yerine yenisini koymak zorundadır. Deney süresince başka grupların malzemelerini almayınız ve kendi malzemelerinizi başka gruplara vermeyiniz. Diğer grupları rahatsız etmemek ve daha verimli bir çalışma ortamı sağlamak için laboratuarda ALÇAK SESLE konuşmak zorunludur. Deney sırasında gruplar arasında bilgi veya malzeme alış verişi kesinlikle yapılmayacaktır. Cep telefonu, radyo, walkman vs. gibi deney ölçümlerini bozabilecek veya başkalarını rahatsız edebilecek elektronik aletleri laboratuar içinde kapalı tutunuz. Çanta, mont vs. gibi eşyalarınızı deney masasının üzerine koymayınız. Deney sırasında genel ahlak ve temizlik kurallarına uyulmaya özen gösterilmelidir. Deney sonunda deney masası toparlanmalı, ilgili elektrik bağlantıları kesilerek, tabureler ve masa düzenli bir biçimde bırakılmalıdır. Ön çalışma ve deney raporlarında kopya çektiği belirlenen öğrenciler laboratuvar dersinden başarısız olarak değerlendirilir. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 3

DENEYLER YAPILIRKEN DİKKAT EDİLMESİ GEREKEN NOKTALAR Devreleri kurarken gerilim kaynağı mutlaka kapalı olmalıdır. Devreye gerilim verilmeden önce yapılan bağlantıların doğruluğu kontrol edilmeli. Tümdevrelerin besleme ve toprak hatları doğru olarak bağlandı mı? Besleme gerilimi ve toprak hattı arasında kısa devre oluşabilir mi? Tümdevrelerin gerekli olan tüm girişlerine (denetim, izin, saat) bağlantı yapıldı mı? Çıkış olan bir hatta yanlışlıkla giriş işareti uygulanmış olabilir mi? İki çıkış yanlışlıkla kısa devre edilmiş olabilir mi (Açık kollektörlü ve 3 konumlu geçitler dışında)? Bağlantılar deneyde istenen işlemi gerçekleştirmek üzere doğru olarak yapıldı mı? Tüm bağlantıların doğruluğundan emin olduktan sonra devreye besleme gerilimi verilmeli. Eğer devre beklendiği gibi çalışmıyorsa hemen besleme gerilimi kapatılarak devre kontrol edilmeli. Kontrol işleminde 2. Maddede belirtilen noktalara dikkat edilmeli. Doğru çalıştığından şüphe edilen elemanların devre ile bağlantıları kesilmeli ve bu elemanlar ayrı olarak test edilmelidir. Devre üzerinde değişiklik yapılırken (eleman ekleme/çıkarma, bağlantı değiştirme) gerilim kaynağı mutlaka kapalı olmalıdır. Tüm sınamalara karşın hata bulunamıyorsa laboratuvarda görevli asistanlardan yardım istenmelidir. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 4

RAPOR YAZIM KILAVUZU Laboratuvar raporları, bilimsel bir çalışmada elde edilen sonuçları sunmak üzere aşağıdaki kurallara uygun olarak hazırlanacaktır. Grup elemanları her deneyden sonra ortak bir grup raporu hazırlayacaklardır. Raporlar beyaz A4 kâğıtlarının tek yüzüne, mümkünse bilgisayar ile ya da okunaklı bir el yazısı ile yazılarak hazırlanacaktır. Çizimler bilgisayar ya da cetvel kullanarak yapılacaktır. Raporlar, deneyi yapan tüm öğrencilerin isimlerin, imzalarının, tarih ve e-mail adreslerinin yer aldığı tek tip kapak sayfası ile başlayacaktır. Bunların dışında farklı yapılarda kapaklar kullanmayınız. Raporlar deneyin yapıldığı tarihten bir hafta sonra deney saatinde teslim edilmelidir. Teslim zamanından daha geç getirilen raporlar, geç getirilen her hafta için %50 not indirimine uğrayacaktır. Teslim edilmeyen raporların notu sıfır olarak belirlenecektir. Raporlar aşağıdaki bölümlerden oluşacaktır: Amaç: Deneyde hangi konuların incelenmesi ve öğrenilmesi amaçlanmaktadır? Her deney bölümü için: Devre Çizimleri: Deneylerde kurduğunuz devrelerin lojik çizimi raporda yer alacaktır. Devreler çizilirken lojik kapılar için (AND, NAND, OR, NOR vs.) lojik simgeler kullanılacaktır. Simgelerin üstüne bu kapının hangi entegre ile gerçeklendiği yazılacaktır. Aşağıdaki örnekte bir NAND kapısının çizimi gösterilmiştir. Simgenin üstündeki yazının anlamı: 74LS00 entegresinin içindeki 4 adet NAND kapısından ikincisi kullanılmıştır. Eğer devrede aynı entegreden birden fazla kullanılmışsa bunlar da kendi aralarında numaralanarak gösterilecektir. Örneğin; #2,74LS05, 1/6 gibi. Ve kullanılan bacak bağlantı numaralarının lojik simgeler üzerine yazılmalıdır. 4 5 74LS00, 2/4 6 Daha karmaşık yapıdaki elemanlar (sayıcı, flip-flop, saklayıcı gibi) ise blok diyagram olarak gösterilecektir. Bu diyagram üstünde elemanların kullanılan uçları katalogtaki isimleri ile belirtilecektir. Sonuçlar: Deneyin her bölümü için elde edilen sonuçlar (tablo, çizim, gözlem) düzgün ve okunaklı bir şekilde yazılacak ve yorumlanacaktır. Eğer deneyde istenmişse teorik olarak beklenen değerler ile deneyde elde edilen sonuçlar karşılaştırılacaktır. Raporda sonuçların ne şekilde verileceği deney kılavuzlarının sonunda yer alan Raporda İstenenler bölümünde belirtilmiştir. Tamamlayamadığınız bölümler için de beklenen sonuçları yazınız. Sorular: Raporda İstenenler bölümünde sorulan soruların cevapları rapora yazılacaktır. Yorum ve Görüşler: Öğrenciler deneyle ilgili yorum ve görüşlerini bu bölüme yazabilirler. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 5

EGE UNIVERSITY ELECTRICAL & ELECTRNONICS ENGINEERING DEPARTMENT LOGIC CIRCUITS LABORATORY EXPERIMENT REPORT EXPERIMENT NO: EXPERIMENT: DATE OF EXPERIMENT : DATE OF REPORT : GROUP: No Name Surname E-mail Signature 1) 2) 2017 Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 6

Equipments List 7400 Quad 2-input NAND (contains four NAND gates) (1) 7402 Quad 2-input NOR (contains four NOR gates) (1) 7404 Hex Inverter (contains six inverters) (1) 7408 Quad 2-input AND (contains four AND gates) (1) 7432 Quad 2-input OR (contains four OR gates) (1) 74LS76 Dual J-K Master Slave Flip/Flop (2) 7486 Quad 2-input XOR (contains four XOR gates) (1) 74LS153 Dual 4 Input Multiplexer (2) 74LS194 4 Bit Bi-Directional Universal Shift Register (1) Experiment No Equipments List 1-2 7400 (1) 3 7404 (1), 7408 (1), 7432 (1) 4 7402 (1), 7404 (1), 7408 (1), 7432 (1) 5 7404 (1), 7408 (1), 7432 (1), 7486 (1) 6 7404 (1), 74153 (2) 7 7404 (1), 7476 (2) 8 7404 (1), 7408 (1), 7432 (1), 7476 (2) 9 74153 (1), 7476 (2) 10 7404 (1), 74194 (1) DIGIBOARD 2013 Malzemeleri R1, R2, R3, R4, R5, R6, R7, R8: 330 Ω ¼ Watt Metal Film Direnç RA: 2k2 Ω ¼ Watt Metal Film Direnç R9: 1k Ω ¼ Watt Metal Film Direnç SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8: Sürgülü On/Off Anahtar 180 K1, K2, K3, K4, K5, K6, K7, K5, K9, K10: 2 pin 1 No Yeşil Klemens (5mm.) U1: LM555 Entegresi C4, C1, C2: 10uF 25V Kutuplu Kondansatör 7805: LM7805 Regülatör LD1, LD2, LD3, LD4, LD5, LD6, LD7, D9: 3MM Kırmızı Led D10:1N4001 Diyot FRQ: 10k Ω vidalı çok turlu dik trimpot 9V Jack: Power Giriş Konnektörü Şase Tip ( 2.5MM ) Ek Malzemeler: 9V Adaptör Breeadboard Regülatör Soutucu Kılıfı 8 pin Entegre Soketi Tekli Bread Board Notlar: U1: 555 entegresi lehimlenmeden sadece 8 pin dip soketi takılıp lehimlenerecektir. Entegrenin oyuk tarafı aşağı doğru bakacaktır. Sokete monte edilecektir. C4, C1, C2: 10uF olup düz çizgili eksi tarafları ledlerin olduğu tarafa doğru bakacaktır. 7805: LM7805 Regülatörü önce soğutucusu vidalanıp sonra boarda monte edilecektir. Adaptör: Adaptör için 9V çıkışlı en az 250mA adaptör kullanılacaktır. (Orta Ucu +) Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 7

LAB #1: EXPERIMENT SET Aim: In this experiment, you will learn how to use the logic circuits experiment set and other devices. Preliminary study: The following sets of functions are available on the experiment kit given above: +5V, GND supply voltage 8 Leds 8 Switches Clock signal generator Before you come to the lab, research the following and prepare a preliminary study report. 1. What is LED? 2. What is the supply voltage? 3. What is the function of the 7805? Where is it used? 4. What does clock generator, frequency and period mean? Experiment Study: Perform the following operations. 1. Turn on and off each LED using all switches. 2. Calculate the frequency of the clock for 1 Hz and 50 Hz, and plot the oscilloscope view. Observe the light of the LED. Check the effect by changing the frequency. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 8

LAB #2: LOGIC GATES Aim: In this experiment, the aim is to experiment with the functions of learning to use the integrated logic gates. Preliminary study: Examine the data sheets (datasheets) of the following integrated circuits and find out their leg connections, how many volt supply voltage they are operating and their logic functions. Learn about the truth table of the following gates. 7400 NAND 7402 NOR 7404 NOT 7486 XOR Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Experiment Study: Perform the following procedure with the experiment kit. 1. Verify the accuracy of the 2-input NAND gate using 2 switches and an LED. 2. Obtain the NOT gate using the NAND gate. Verify the truth table of the NOT gate using 1 switch and one LED. 3. Obtain the AND gate using the NAND gate. Verify the truth table of the AND gate using 2 switches and one LED. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 9

LAB #3: BASIC LOGIC FUNCTION Aim: In this experiment, the objective is to experiment with logic gates and to experiment with their functions by learning how to implement a desired logic function. Preliminary study: Draw the relevant logic expressions of the following statements. 1. x + x 2. x.x 3. x.y+x.y 4. ((x+x ) +(y+y )) 5. x.y+x.y = (x.y+(x.y )) 6. Get the truth table of the function; x. y+y.z 7. Get the truth table of the function; (x+y ).(z +t ) Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Experiment Study: Prepare the circuits of functions 3, 5 and 7 from the expression given. Discussion: Compare the theoretical and experimental results. Your Name: Date: Have your TA verify the results after completion of each part. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 10

LAB #4: NAND, NOR IMPLEMENTATION EXPERIMENTS In this experiment you will use properties of Boolean algebra to minimize the number of chips in the implementation of Boolean functions. The NAND and NOR gates are said to be universal gates because any digital system can be implemented with NAND or NAND gates alone. PRELAB. 1.- Given the Boolean function: f1 ( w, x, y ) = ( w x ) + ( x y ) a. Draw and fill out the truth table for the function f1 b. Use Boolean algebra to represent f1 using only the Boolean operator NAND. c. Draw the circuit diagram that implements f1 using only NAND gates. d. Using Circuit Maker, implement the function f1 using 74LS00 gates only. e. Verify that the circuit satisfies the truth table. 2.- Given the Boolean function: f2 ( w, x, y ) = ( w + x ) ( x + y ) a. Draw and fill out the truth table for the function f2 b. Use Boolean algebra to represent f2 using only the Boolean operator NOR. c. Draw the circuit diagram that implements f2 using only NOR gates. d. Using Circuit Maker, implement the function f2 using 74LS02 gates only. e. Verify that the circuit satisfies the truth table. Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. EXPERIMENT. Implement on your breadboard the functions f1 (w, x, y) using only NAND and f2 (w, x, y) using only NOR gates. You should be able to use only one chip to implement each function. Verify your circuit, and record the truth table in the Result sheet. When your circuits work properly, have your instructor or TA verify the results and sign on the Result sheet. DISCUSSION. Discuss the advantages of using NAND and NOR gates over the other gates of TTL family. Your Name: Date: Have your TA verify the results after completion of each part. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 11

LAB #5: ITERATIVE 2-BIT SUBTRACTER Implement a three bit subtracter, using the single bit full adder studied in class. Build the circuit with the minimum number of chips possible, test it and show that it operates correctly. Note: To minimize problems with the wiring up of your circuit, follow the steps: i) Wire up the first block of your circuit, verify the correctness of the 1-bit full adder truth table. ii) Wire up the second block, verify that this block also satisfy the truth table iii) Wire up the third block and verify the truth table Once that each of the blocks is working separately, connect them to form the 2-bit full subtracter. Verify that your design is working properly doing the following additions (or any others given by the TA or instructor): 11-10 = 01; 01-01 = 00; 11-01 = 10; 11-00 = 11 Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. PRE LAB. Before going to the lab be sure that you have the following: 1.- The truth table of the 1-bit full-adder 2.- The mathematical expression for the 1-bit full-adder 3.- The reduced expressions for the output variables: Si, and Cout 4.- The circuit diagram of the 2-Bit Adder, showing the chip and pin numbers. DISCUSSION. Discuss the operation of the adder and subtracter. Your Name: Date Have your TA verify the results after completion of each part. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 12

LAB #6: USING DATA SELECTORS 4-BIT ADDER In this experiment you will design and implement a 2-bit adder using multiplexers. You will design first a 1-bit full adder, and then, you will connect four 1-bit full adders in series. The block diagram of your system is: You will use 74LS153 plus whatever gates you need. Minimize the total number of chips. When your adder works correctly, have your lab TA or instructor sign the results sheet. Verify that your design is working properly doing the following additions (or any others given by the TA or instructor): 00 + 11 = 011; 01 + 11 = 100; 11 + 00 = 011; 011 + 011 = 110; Pre Lab. Before going to the lab be sure that you have the following: 1.- The truth table and mathematical expression of the 1-bit full-adder. 2.- The implementation of the output functions: Si, and C out using multiplexers for your 1-bit full adder. 3.- Connect in series four of the 1-bit full adder to obtain the 2-bit adder. You have to connect the Carry-out from the previous stage to the Carry-in of the following stage. For the least significant bit, the Carry-in is zero. 4.- The circuit diagram of the 2-Bit Adder, showing the chips and pin numbers. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 13

Truth Table observed from circuit: b3 b2 b1 b0 a3 a2 a1 a0 Cout S3 S2 S1 S0 Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Your Name: Date Have your TA verify the results after completion of each part. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 14

LAB #7: FLIP-FLOPS AND ASYNCHRONOUS COUNTERS Part A. FLIP-FLOPS In this part of the experiment you will work with JK Flip-flops: J-K edge-triggered Flip-flop: you will use the chip 74LS76 and you will verify its function. Note: Test your circuits and obtain the functional table, and observe how the outputs respond to the change of level on the control signal (clk). Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Edge -Triggered J-K Flip-Flop Use a 74LS76 and verify that this is a positive edge-triggered JK Flip-flop. Get the data sheet for 74LS76 and be sure that you identify and understand all the input and output pins in the chip. Find the State Table for this device, and record the results in the result section. Have your TA verify the results of your circuit. Note: The Set and Clr inputs must be connected to logic 1 for reliable operation. Part B. ASYNCHRONOUS COUNTERS In this part of the experiment you will use JK Flip-Flops (74LS76 or 74LS73) to implement two mod 16 asynchronous counters shown in figures 3 and 4. One of the counters will count up, and the other will count down. These asynchronous counters are also called "ripple counters" or "ripple-through counters", this name describes the action better. The disadvantage of this type of counters is that when we have large counters, there is a significant delay as the signal "ripples through" the various stages. PRELAB. Before going to the lab, draw the time diagrams for the circuits shown in figures 3 and 4.Specify the sequence of each counter. Figure 3. Mod 16 counter (down-counter) Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 15

Figure 4. Mod 16 counter (up-counter) Implement on your breadboard the mod 16 counters of figures 3 and 4, and once they work properly show them to your TA or instructor and get the witness signature. Fill out the an time diagrams for figures 3 and 4 in your reports. Your Name: Date: Have your TA verify the results after completion of each part. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 16

LAB #8:UP/DOWN COUNTER In this lab you have to design and implement a synchronous counter that follows the sequence: UP: 0-1-2-3-4-5-0, DOWN: 5-4-3-2-1-0-5. For your design you will use J-K Flip-Flops (74LS76 or 74LS73) and any additional gates. Minimize the number of chips in your implementation. DESIGN i) Design a 3-bit Up/Down counter that will follow the sequence: Up: 0-1-2-3-4-5-0.. Down: 5-4-3-2-1-0-5.. Your design will have two inputs: the Clock, and the U/D pin. With the U/D pin you will choose the direction of counting. Minimize the number of chips, and draw a neat and well label circuit diagram for both designs. The counter must be designed as self starting in case when it enters any of unwanted states. ii) Connect 1kHz square pulse for the clock pulse and by using CRO observe and draw the stage of each stage. Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. PHYSICAL IMPLEMENTATION. Implement your design on your breadboard. Test your circuit, and verify that the time diagram of your design it is correct. Be sure that your lab report shows all the steps in your design, in a neat and clear way. In particular, verify that it includes the following: State Diagram Transition Table Circuit diagram DISCUSSION Compare theoretical result and experimental result. Your Name: Date: Have your TA verify that your counter follows the correct sequence, UP and DOWN. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 17

LAB #9: REGISTER DESIGN Aim: The purpose of this experiment is to identify the register internal structure. Preliminary study: Register Design: Design using a 2-bit bidirectional shift register, multiplexer and flip-flops. Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Experimental Study: 1. Register Design: Perform a 2-bit bidirectional shift register in the lab. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 18

LAB #10: SHIFT REGISTERS Aim: The purpose of this experiment is to examine the properties of shift registers. Preliminary study: 1. Register Usage: Using one register (74HC194), set up circuits that perform the following operations separately at every clock pulse a) Rotate right b) Rotate left c) Shift right d) Shift left 2. Johnson Counter Design the johnson counter using a 4-bit shift register. Clock 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 Simulation study: Simulate the experimental circuit in the Proteus program and find the desired results in the experiment and add them to the preliminary work. Give the experimental results together with the results obtained in the simulations. Experimental Study: 1. Examination of Shift Register functions: Setup the "Rotate right" and "Shift left" circuits you designed. 2. Register application Setup the " Johnson Counter" circuits you designed. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 19

GUIDE TO ASSEMBLING YOUR CIRCUITS In this section we describe the use of the breadboard and give basic hints about the wiring process needed to power up and interconnect your circuits. Assembling circuits on your breadboard is a fast and easy process once you get used to it. To assemble your circuit first select the chips that you need, insert them in the breadboard, wire up the power and ground connections as described in the next section and next wire the logic elements according to the circuit connections that you obtained from the design process. Before you insert a chip into the breadboard, make sure it is properly oriented (see Fig. 1 & 2), and that when you press it down the pins of the chip actually enter the holes and do not bend underneath the chip package. When wiring, be careful to hit the right hole needed in the connection, because this is one of the most common mistakes found to cause an error in your projects. 1.1. Breadboard Description. In order to assemble the lab experiments, every student should use his/her own breadboard (similar to the one shown in Figure 1). The breadboard has 8 sets of rows (1) and (2), consisting of 25 holes that are horizontally interconnected. I also contains groups of columns (3) and (4), consisting of 5 holes that are vertically interconnected. The rows and columns are used to hold chips and wires, and interconnect them as shown in Figures 2 and 3. 3 Fig. 1. - Breadboard Also, in Figures 2 and 3 we show two typical ways to distribute power (1), and ground (2) signals that are recommended in order to avoid noise in your circuit, and assure good performance from the chips. The banana plugs (3), if available, can be used to connect your breadboard to an external power supply. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 20

Fig. 2. - Power and Ground Connection (method A) Fig. 3. - Power and Ground Connection (method B) A breadboard is used for holding logic chips and wires that connect them together in order to realize a desired circuit. There are two types of common connections on the breadboard: 1. 5-pin connections (busses) which run vertically (as shown in fig. B.1a) on the board 2. 50-pin connections (busses) which run horizontally (as shown in fig. B.1a) on the board. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 21

What is meant by common connections is that a row or column of common pins will have the same voltage as each other (or same logic state). This common connection will allow multiple connections to be made at the same pin on a logic chip. When placing a logic chip on the board, place it over the gap between the two sets of 5-pin connection (if it is done properly, it will fit right). To make a connection between two pins, or the D/A breadboard, take a wire and insert it in one of the common pinholes to the other desired pin. Figure B1.a shows a close up view of the breadboard indicating the connectivity of the 5 pin and 50 pin busses. Figure B1.b shows a 14 pin integrated circuit plugged into the breadboard (note how the integrated circuit straddles the white area between the 5 pin busses). Figure B1.c shows an offboard wire plugged into one of the 50 pin horizontal bus, then a short wire connecting the 50 pin bus to the 5 pin bus corresponding to pin #14. Figure B1.c also shows a short wire connecting pins 3 and 5 of the integrated circuit. Figure B.1a: Close up view of a portion of a breadboard 5 pin holes connected vertically (see arrows) Two row busses are connected horizontally (see arrows) Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 22

Fig B.1b: 14 pin Integrated Circuit plugged into Breadboard Fig B.1c: Wire Connections, off board wire connected to pin #14, Pin #3 connected to Pin #5. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 23

1.2. - TTL Packages Description. The chips or packages that will be used to build the experiments belong to the TTL logic family, and they are referred as the 74LSXX family, where the XX is a number that indicates the specific type of gate or function. The main characteristics for some typical logic gates packages are shown in Figures 4 and 5 next. Fig. 4. - Inverter (NOT) gate pin distribution Fig. 5. - AND gate pin distribution Most commonly used TTL devices have their power and ground connections on pins 14 and 7 respectively, however verify this information before using some special function or uncommon Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 24

packages. Also, all packages have a notch or mark that indicates the proper orientation of the device. From this mark each pin is numbered in a counter clockwise direction. The specific function that each chip performs is typically described using function tables, logic tables or logic diagrams as the ones shown in Figure 6. Fig. 6. - Typical Manual Descriptions for a TTL Gate. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 25

Digital TIPS: TTL vs CMOS The 74LS series TTL chips are very useful for most applications: Fast, ~10 ns gate delay Fairly low power consumption, ~1 mw/gate Widely established standard The 74HC CMOS series eliminates many old objections to CMOS Slightly Faster than 74LS TTL ~< 10 ns much better than older 4000 and 74C chips Power consumption less than LS TTL at 1 MHz but power exceeds LS as frequency increases above 1 MHz More robust against abuse (static electricity etc) Logic thresholds not consistent with standard TTL Can use HCT chips which have TTL logic thresholds Can Run HC CMOS at 3.3V supply for level compatibility, 40% slower 4000 and 74C CMOS allow wide range for supply voltage: 3 V ¾ V CC ¾ 13 V -->performance better at higher voltages, 9V recommemded Interfacing TTL and CMOS CMOS to TTL If V CC is +5V, then one CMOS output can drive one LS TTL input CMOS logic levels are close to 0 V or 5 V, so no threshold incompatibility If CMOS is run at V CC ~3.3 V, thresholds are still compatible with TTL Sometimes 4000 series or 74C chips are run at V CC > 5 V for improved speed Need level-shifter chip to interface to TTL, for example 4049/50, 74C901/2 TTL to CMOS TTL output thresholds are inconsistent with 74HC, 74C and 40' CMOS inputs When CMOS is run with V CC = 5 V Use a 74HCT buffer between them Use an open collector buffer with pullup to 5 V When CMOS uses V CC = 3.3 V (Usually 74HC only) Direct connection from TTL to CMOS possible When CMOS uses V CC > 5 V (Usually 4000 or 74C series< use level shifter buffer chip 40109, LTC1045, 14504 or use open collector buffer with pullup to 5 V Common Precautions Noisy supply and ground lines can cause troubles that take hours to find. Make V CC wire very large so that current surges don't cause much voltage drop Make a large bus wire, don't daisy chain V CC or ground lines Be very careful with grounding. Typical precautions are Ground all devices at one single point Use a ground plane one side of pc board a solid conductor for gnd connections Both V CC and ground lines should be wide traces or #14 or #16 wire to minimize both inductance and resistance Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 26

Quirks with TTL Draws a lot of current when switching. Put despiking capacitors between V SIZE=2> CC and gnd on every 2nd or 3rd chip to supply large current surges momentarily 0.01 µf to 0.1µF, ceramic 1 to 47 µf tantalum cap between wherev CC and gnd comes on board. Noise immunity to low level is very bad with TTL -->always check for noise on gnd Quirks with CMOS Input FET very easy to ruin Be very careful of static charge Discharge yourself before touching store and transport in conductive foam or pouch never put belly up Never plug in or unplug them with supply on Will "latch up" if an input is driven above supply V CC V CC shorts to ground, chip gets hot, pretty soon it's belly-up Unconnected inputs are indeterminate Connect all inputs of all gates on a chip, even if the gates aren't used. Failure to do this could make both complementary FETS conducting Draws a lot of current messing up other gates and chips If you forget to connect V CC, or gnd, chip will still work as long as at least one pin is at V CC or gnd. Unconnected inputs and unconnected supply lines can cause intermittent and unreproducible failures that drive you up a wall. Driving External devices: CMOS and TTL are designed to sink more current than source Put any device that draws current between V CC and the output Use a current limiting resistor for LEDs (220 to 1k) For 5 V relays, always use diode to protect against inductive spike If you need more current (>10 ma) use gate output to drive a transistor If large transients are apt to come from a device, use optoisolator Open collector or drain outputs can be used for nonstandard voltages Sending signals over a distance Use an output buffer on sender and input Schmitt trigger on receiver Open collector or special line driver senders ensure clean levels Terminate line just before Schmitt trigger Eliminates reflections 180 to 5V, 390 to gnd is standard (H&H Fig 9.32) Twisted pair line with differential input (H&H Fig. 9.34) Higher voltage signals using twisted pair (RS232) RS422 combines differential signal and higher signal voltages Current sinking drivers Uses current sources to drive line (H&H say works real good, see Fig 9.35) Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 27

Coaxial cable Good interference immunity Data rates up to 100 kb/s over 1 mile (1.6 km) Well standardized See H&H Fig 9.40,41,42 for examples Fibre optic cable Standardized senders, receivers and cables available Cheap Infrared LED sender ($1) Phototransitor receiver ($1) 1mm plastic step-index cable (cheap) 1Mb/s over 30 ft Better system 200µm glass step index fibre Detectors have builtin amps 5Mb/s over 1 km Current record (old?) 4 GHz over 120 km, no repeaters Reference: http://www.sfu.ca/phys/430/ttlcmostips.html Datasheets:http://www.datasheetcatalog.com, http://www.hanssummers.com/electronics/datasheets/ The 555 Timer IC The 555 timer IC is an amazingly simple yet versatile device. It has been around now for many years and has been reworked into a number of different technologies. The two primary versions today are the original bipolar design and the more recent CMOS equivalent. These differences primarily affect the amount of power they require and their maximum frequency of operation; they are pin-compatible and functionally interchangeable. The pin connections are as follows: 1. Ground. 2. Trigger input. 3. Output. 4. Reset input. 5. Control voltage. 6. Threshhold input. 7. Discharge. 8. +V CC. +5 to +15 volts in normal use. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 28

If we rearrange the circuit slightly so that both the trigger and threshhold inputs are controlled by the capacitor voltage, we can cause the 555 to trigger itself repeatedly. In this case, we need two resistors in the capacitor charging path so that one of them can also be in the capacitor discharge path. This gives us the circuit shown to the left. In this mode, the initial pulse when power is first applied is a bit longer than the others, having a duration of 1.1(Ra + Rb)C. However, from then on, the capacitor alternately charges and discharges between the two comparator threshhold voltages. When charging, C starts at (1/3)V CC and charges towards V CC. However, it is interrupted exactly halfway there, at (2/3)V CC. Therefore, the charging time, t1, is -ln(1/2)(ra + Rb)C = 0.693(Ra + Rb)C. When the capacitor voltage reaches (2/3)V CC, the discharge transistor is enabled (pin 7), and this point in the circuit becomes grounded. Capacitor C now discharges through Rb alone. Starting at (2/3)V CC, it discharges towards ground, but again is interrupted halfway there, at (1/3)V CC. The discharge time, t2, then, is -ln(1/2)(rb)c = 0.693(Rb)C. The total period of the pulse train is t1 + t2, or 0.693(Ra + 2Rb)C. The output frequency of this circuit is the inverse of the period, or 1.44/(Ra + 2Rb)C. Note that the duty cycle of the 555 timer circuit in astable mode cannot reach 50%. On time must always be longer than off time, because Ra must have a resistance value greater than zero to prevent the discharge transistor from directly shorting V CC to ground. Such an action would immediately destroy the 555 IC. Electrical & Electrnonics Engineering Department, Logic Circuits Laboratory 29