Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Ana Modul -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; Library U ISIM; use U ISIM.vcomponents.all; entity ana_modul is port( clock end ana_modul; : in std_logic; clr_pc : in std_logic; clr_reg : in std_logic; clr_memory : in std_logic; counter : out std_logic_vector(14 downto 0 Data : out std_logic_vector(15 downto 0) architecture Behavioral of ana_modul is component kontrol_unitesi port(v,c,n,z,clk,clr : in std_logic; mb,md,rw,mw : out std_logic; da,ba,aa : out std_logic_vector(3 downto 0 fs : out std_logic_vector(4 downto 0 end component; ci : out std_logic_vector(15 downto 0 counter : out std_logic_vector(14 downto 0) 0) component veri_yolu Port(Clock,MB,MD,RW,reg_clr: in std_logic; DA,AA,BA : in std_logic_vector(3 downto 0 FS : in std_logic_vector(4 downto 0 Constant_In,Data_In : in std_logic_vector(15 downto 0 Vo,Co, o,zo : out std_logic; Adress_Out,Data_Out : out std_logic_vector(15 downto 0 Data : out std_logic_vector(15 downto end component; 1
Kaynak Kodları -- component bellek -- port( mw,clk,clr : in std_logic; -- data_in : in std_logic_vector(15 downto 0 -- adress_in : in std_logic_vector(5 downto 0 -- data_out : out std_logic_vector(15 downto 0) -- -- end component; signal ara : std_logic_vector(24 downto 0 signal con,add,dat_o,dat_i : std_logic_vector(15 downto 0 Modul1:veri_yolu port map( Data=>Data, reg_clr=>clr_reg, Clock=>clock, MB=>ara(12), MD=>ara(6), RW=>ara(5), DA=>ara(24 downto 21), AA=>ara(16 downto 13), BA=>ara(20 downto 17), FS=>ara(11 downto 7), Vo=>ara(3),Co=>ara(2), o=>ara(1),zo=>ara(0), Constant_In=>con, Data_In=>dat_i, Adress_Out=>add, Data_Out=>dat_o Modul2:kontrol_unitesi port map( counter=>counter, v=>ara(3), c=>ara(2), n=>ara(1), z=>ara(0), clk=>clock, clr=>clr_pc, da=>ara(24 downto 21), ba=>ara(20 downto 17), aa=>ara(16 downto 13), fs=>ara(11 downto 7), ci=>con, mb=>ara(12), md=>ara(6), rw=>ara(5), mw=>ara(4) 2
Tek Vuruşluk Đşlemci -- modul3:bellek -- port map( -- clr=>clr_memory, -- mw=>ara(4), -- clk=>clock, -- data_in=>dat_o, -- adress_in=>add(5 downto 0), -- data_out=>dat_i -- -- RAMB16_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Single-Port RAM -- Xilinx HDL Language Template, version 9.2i RAMB16_S18_inst : RAMB16_S18 generic map ( I IT => X"00000", -- Value of output RAM registers at startup SRVAL => X"00000", -- Ouput value upon SSR assertion WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or O_CHA GE -- The following I IT_xx declarations specify the intial contents of the RAM -- Address 0 to 255 --... I IT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 511 I IT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", 3
Kaynak Kodları I IT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 512 to 767 I IT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 768 to 1023 I IT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", I IT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of I ITP_xx are for the parity bits -- Address 0 to 255 I ITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", I ITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 511 I ITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", I ITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 512 to 767 I ITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", I ITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 768 to 1023 I ITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", I ITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DO => dat_i, -- 16-bit Data Output 4
Tek Vuruşluk Đşlemci -- DOP =>, -- 2-bit parity Output ADDR => add(9 downto 0), -- 10-bit Address Input CLK => clock, -- Clock DI => dat_o, -- 16-bit Data Input DIP => "XX", -- 2-bit parity Input E => '1', -- RAM Enable Input SSR => clr_memory, -- Synchronous Set/Reset Input WE => ara(4) -- Write Enable Input -- End of RAMB16_S18_inst instantiation end Behavioral; 5
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Veri Yolu -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity veri_yolu is Port ( Clock : in std_logic; reg_clr : in std_logic; DA : in std_logic_vector(3 downto 0 AA : in std_logic_vector(3 downto 0 BA : in std_logic_vector(3 downto 0 MB : in std_logic; FS : in std_logic_vector(4 downto 0 MD : in std_logic; RW : in std_logic; Constant_In : in std_logic_vector(15 downto 0 Data_In : in std_logic_vector(15 downto 0 Adress_Out : out std_logic_vector(15 downto 0 Data_Out : out std_logic_vector(15 downto 0 Vo : out std_logic; Co : out std_logic; o : out std_logic; Zo : out std_logic; Data : out std_logic_vector(15 downto 0) end veri_yolu; architecture Behavioral of veri_yolu is -- COMPO E T fonksiyon_unitesi2 -- PORT( -- A : I std_logic_vector(15 downto 0 -- B : I std_logic_vector(15 downto 0 -- FS: I std_logic_vector(4 downto 0 -- F : OUT std_logic_vector(15 downto 0 -- V : OUT std_logic; -- C : OUT std_logic; -- : OUT std_logic; -- Z : OUT std_logic -- E D COMPO E T; COMPO E T Fonksiyon_Unitesi 6
Tek Vuruşluk Đşlemci PORT( A_Girisi : I std_logic_vector(15 downto 0 B_Girisi : I std_logic_vector(15 downto 0 FS : I std_logic_vector(4 downto 0 Elde_Girisi : I std_logic; Sonuc : OUT std_logic_vector(15 downto 0 V : OUT std_logic; C : OUT std_logic; : OUT std_logic; Z : OUT std_logic E D COMPO E T; -- COMPO E T yazmac_unitesi -- PORT( -- CLK,reg_clr : I std_logic; -- DA : I std_logic_vector(3 downto 0 -- AA : I std_logic_vector(3 downto 0 -- BA : I std_logic_vector(3 downto 0 -- WRITE : I std_logic; -- DATA : I std_logic_vector(15 downto 0 -- A_data : OUT std_logic_vector(15 downto 0 -- B_data : OUT std_logic_vector(15 downto 0) -- -- E D COMPO E T; COMPO E T yazmac_dosyasi PORT( clk : I std_logic; temizle : I std_logic; da : I std_logic_vector(3 downto 0 aa : I std_logic_vector(3 downto 0 ba : I std_logic_vector(3 downto 0 yaz : I std_logic; gelen_bilgi : I std_logic_vector(15 downto 0 a_bilgisi : OUT std_logic_vector(15 downto 0 b_bilgisi : OUT std_logic_vector(15 downto 0) E D COMPO E T; COMPO E T mux16_bit PORT( bir : I std_logic_vector(15 downto 0 sifir : I std_logic_vector(15 downto 0 cikis : OUT std_logic_vector(15 downto 0 secim : in std_logic E D COMPO E T; signal B_s,A_A_A,c_Do,F_s,c_d_D: std_logic_vector(15 downto 0 7
Kaynak Kodları -- Modul1: yazmac_unitesi -- PORT MAP -- ( -- DA => DA, -- AA => AA, -- BA => BA, -- reg_clr => reg_clr, -- CLK => Clock, -- WRITE => RW, -- DATA => c_d_d, -- A_data => A_A_A, -- B_data => B_s -- Inst_yazmac_dosyasi: yazmac_dosyasi PORT MAP( clk => Clock, temizle => reg_clr, da => DA, aa => AA, ba => BA, yaz => RW, gelen_bilgi => c_d_d, a_bilgisi => A_A_A, b_bilgisi => B_s Modul2_MUXB: mux16_bit port map ( bir=>constant_in, secim=>mb, sifir=>b_s, cikis=>c_do -- Modul3: fonksiyon_unitesi2 -- PORT MAP -- ( -- FS =>FS, -- V =>Vo, -- C =>Co, -- => o, -- Z =>Zo, -- A =>A_A_A, -- B =>c_do, -- F =>F_s -- Inst_Fonksiyon_Unitesi: Fonksiyon_Unitesi PORT MAP( A_Girisi => A_A_A, B_Girisi => c_do, 8
Tek Vuruşluk Đşlemci FS => FS, Elde_Girisi => '0', Sonuc => F_s, V => Vo, C => Co, => o, Z => Zo end Behavioral; Modul4_MUXD:mux16_bit port map ( secim=>md, bir=>data_in, cikis=>c_d_d, sifir=>f_s Adress_Out<=A_A_A; Data_Out<=c_Do; Data<=c_d_D; 9
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Yazmac Dosyası -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity yazmac_dosyasi is Port ( clk : in STD_LOGIC; temizle : in STD_LOGIC; da : in STD_LOGIC_VECTOR (3 downto 0 aa : in STD_LOGIC_VECTOR (3 downto 0 ba : in STD_LOGIC_VECTOR (3 downto 0 yaz : in STD_LOGIC; gelen_bilgi : in STD_LOGIC_VECTOR (15 downto 0 a_bilgisi : out STD_LOGIC_VECTOR (15 downto 0 b_bilgisi : out STD_LOGIC_VECTOR (15 downto 0) end yazmac_dosyasi; architecture Behavioral of yazmac_dosyasi is COMPO E T decoder4to16 PORT( giris : I std_logic_vector(3 downto 0 enable : I std_logic; cikis : OUT std_logic_vector(15 downto 0) E D COMPO E T; COMPO E T mux_16bit_4_bit_secici PORT( giris0 : I std_logic_vector(15 downto 0 giris1 : I std_logic_vector(15 downto 0 giris2 : I std_logic_vector(15 downto 0 giris3 : I std_logic_vector(15 downto 0 giris4 : I std_logic_vector(15 downto 0 giris5 : I std_logic_vector(15 downto 0 giris6 : I std_logic_vector(15 downto 0 giris7 : I std_logic_vector(15 downto 0 giris8 : I std_logic_vector(15 downto 0 giris9 : I std_logic_vector(15 downto 0 giris10 : I std_logic_vector(15 downto 0 giris11 : I std_logic_vector(15 downto 0 giris12 : I std_logic_vector(15 downto 0 giris13 : I std_logic_vector(15 downto 0 10
Tek Vuruşluk Đşlemci giris14 : I std_logic_vector(15 downto 0 giris15 : I std_logic_vector(15 downto 0 secici : I std_logic_vector(3 downto 0 cikis : OUT std_logic_vector(15 downto 0) E D COMPO E T; COMPO E T yazmac PORT( clk : I std_logic; giris : I std_logic_vector(15 downto 0 enable : I std_logic; clr : I std_logic; cikis : OUT std_logic_vector(15 downto 0) E D COMPO E T; type yazmac_ara_baglanti is array (0 to 15) of std_logic_vector(15 downto 0 signal yazmac_to_mux: yazmac_ara_baglanti; --signal yazmac_to_mux: std_logic_vector(15 downto 0 signal decoder_to_yazmac: std_logic_vector(15 downto 0 Inst_decoder4to16: decoder4to16 PORT MAP( giris => da, cikis => decoder_to_yazmac, enable => yaz muxa: mux_16bit_4_bit_secici PORT MAP( giris0 => yazmac_to_mux(0), giris1 => yazmac_to_mux(1), giris2 => yazmac_to_mux(2), giris3 => yazmac_to_mux(3), giris4 => yazmac_to_mux(4), giris5 => yazmac_to_mux(5), giris6 => yazmac_to_mux(6), giris7 => yazmac_to_mux(7), giris8 => yazmac_to_mux(8), giris9 => yazmac_to_mux(9), giris10 => yazmac_to_mux(10), giris11 => yazmac_to_mux(11), giris12 => yazmac_to_mux(12), giris13 => yazmac_to_mux(13), giris14 => yazmac_to_mux(14), giris15 => yazmac_to_mux(15), secici => aa, cikis => a_bilgisi 11
Kaynak Kodları muxb: mux_16bit_4_bit_secici PORT MAP( giris0 => yazmac_to_mux(0), giris1 => yazmac_to_mux(1), giris2 => yazmac_to_mux(2), giris3 => yazmac_to_mux(3), giris4 => yazmac_to_mux(4), giris5 => yazmac_to_mux(5), giris6 => yazmac_to_mux(6), giris7 => yazmac_to_mux(7), giris8 => yazmac_to_mux(8), giris9 => yazmac_to_mux(9), giris10 => yazmac_to_mux(10), giris11 => yazmac_to_mux(11), giris12 => yazmac_to_mux(12), giris13 => yazmac_to_mux(13), giris14 => yazmac_to_mux(14), giris15 => yazmac_to_mux(15), secici => ba, cikis => b_bilgisi Inst_yazmac0: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => '0', clr => temizle, cikis => yazmac_to_mux(0) Inst_yazmac1: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(1), clr => temizle, cikis => yazmac_to_mux(1) Inst_yazmac2: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(2), clr => temizle, cikis => yazmac_to_mux(2) Inst_yazmac3: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(3), clr => temizle, cikis => yazmac_to_mux(3) 12
Tek Vuruşluk Đşlemci Inst_yazmac4: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(4), clr => temizle, cikis => yazmac_to_mux(4) Inst_yazmac5: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(5), clr => temizle, cikis => yazmac_to_mux(5) Inst_yazmac6: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(6), clr => temizle, cikis => yazmac_to_mux(6) Inst_yazmac7: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(7), clr => temizle, cikis => yazmac_to_mux(7) Inst_yazmac8: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(8), clr => temizle, cikis => yazmac_to_mux(8) Inst_yazmac9: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(9), clr => temizle, cikis => yazmac_to_mux(9) Inst_yazmac10: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(10), clr => temizle, cikis => yazmac_to_mux(10) 13
Kaynak Kodları Inst_yazmac11: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(11), clr => temizle, cikis => yazmac_to_mux(11) Inst_yazmac12: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(12), clr => temizle, cikis => yazmac_to_mux(12) Inst_yazmac13: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(13), clr => temizle, cikis => yazmac_to_mux(13) Inst_yazmac14: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(14), clr => temizle, cikis => yazmac_to_mux(14) Inst_yazmac15: yazmac PORT MAP( clk => clk, giris => gelen_bilgi, enable => decoder_to_yazmac(15), clr => temizle, cikis => yazmac_to_mux(15) end Behavioral; 14
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Dekoder -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity decoder4to16 is Port ( giris : in STD_LOGIC_VECTOR (3 downto 0 cikis : out STD_LOGIC_VECTOR (15 downto 0 enable : in STD_LOGIC end decoder4to16; architecture Behavioral of decoder4to16 is cikis(0) <= '1' when enable='0' else '1' when enable='1' and giris="0000" else '0'; cikis(1) <= '1' when enable='1' and giris="0001" else '0'; cikis(2) <= '1' when enable='1' and giris="0010" else '0'; cikis(3) <= '1' when enable='1' and giris="0011" else '0'; cikis(4) <= '1' when enable='1' and giris="0100" else '0'; cikis(5) <= '1' when enable='1' and giris="0101" else '0'; cikis(6) <= '1' when enable='1' and giris="0110" else '0'; cikis(7) <= '1' when enable='1' and giris="0111" else '0'; 15
Kaynak Kodları cikis(8) <= '1' when enable='1' and giris="1000" else '0'; cikis(9) <= '1' when enable='1' and giris="1001" else '0'; cikis(10) <= '1' when enable='1' and giris="1010" else '0'; cikis(11) <= '1' when enable='1' and giris="1011" else '0'; cikis(12) <= '1' when enable='1' and giris="1100" else '0'; cikis(13) <= '1' when enable='1' and giris="1101" else '0'; cikis(14) <= '1' when enable='1' and giris="1110" else '0'; cikis(15) <= '1' when enable='1' and giris="1111" else '0'; end Behavioral; 16
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : 16 bitlik Çoklayıcı -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity mux_16bit_4_bit_secici is Port ( giris0 : in STD_LOGIC_VECTOR (15 downto 0 giris1 : in STD_LOGIC_VECTOR (15 downto 0 giris2 : in STD_LOGIC_VECTOR (15 downto 0 giris3 : in STD_LOGIC_VECTOR (15 downto 0 giris4 : in STD_LOGIC_VECTOR (15 downto 0 giris5 : in STD_LOGIC_VECTOR (15 downto 0 giris6 : in STD_LOGIC_VECTOR (15 downto 0 giris7 : in STD_LOGIC_VECTOR (15 downto 0 giris8 : in STD_LOGIC_VECTOR (15 downto 0 giris9 : in STD_LOGIC_VECTOR (15 downto 0 giris10 : in STD_LOGIC_VECTOR (15 downto 0 giris11 : in STD_LOGIC_VECTOR (15 downto 0 giris12 : in STD_LOGIC_VECTOR (15 downto 0 giris13 : in STD_LOGIC_VECTOR (15 downto 0 giris14 : in STD_LOGIC_VECTOR (15 downto 0 giris15 : in STD_LOGIC_VECTOR (15 downto 0 secici : in STD_LOGIC_VECTOR (3 downto 0 cikis : out STD_LOGIC_VECTOR (15 downto 0) end mux_16bit_4_bit_secici; architecture Behavioral of mux_16bit_4_bit_secici is cikis <= giris0 when secici="0000" else giris1 when secici="0001" else giris2 when secici="0010" else giris3 when secici="0011" else giris4 when secici="0100" else giris5 when secici="0101" else giris6 when secici="0110" else giris7 when secici="0111" else giris8 when secici="1000" else giris9 when secici="1001" else 17
Kaynak Kodları giris10 when secici="1010" else giris11 when secici="1011" else giris12 when secici="1100" else giris13 when secici="1101" else giris14 when secici="1110" else giris15 when secici="1111" else "XXXXXXXXXXXXXXXX"; end Behavioral; 18
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Yazmac -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity yazmac is Port ( clk : in STD_LOGIC; giris : in STD_LOGIC_VECTOR (15 downto 0 enable : in STD_LOGIC; clr : in STD_LOGIC; cikis : out STD_LOGIC_VECTOR (15 downto 0) end yazmac; architecture Behavioral of yazmac is process(clr,clk,giris) if clr ='1' then cikis <= "0000000000000000"; elsif clk'event and clk='0' then if enable='1' then cikis <= giris; end if; end if; end process; end Behavioral; 19
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Fonksiyon Unitesi -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity Fonksiyon_Unitesi is Port ( A_Girisi : in STD_LOGIC_VECTOR (15 downto 0 B_Girisi : in STD_LOGIC_VECTOR (15 downto 0 FS : in STD_LOGIC_VECTOR (4 downto 0 Elde_Girisi: in STD_LOGIC; Sonuc : out STD_LOGIC_VECTOR (15 downto 0 V : out STD_LOGIC; C : out STD_LOGIC; : out STD_LOGIC; Z : out STD_LOGIC end Fonksiyon_Unitesi; architecture Behavioral of Fonksiyon_Unitesi is COMPO E T ALU PORT( A_girisi : I std_logic_vector(15 downto 0 B_girisi : I std_logic_vector(15 downto 0 Secici : I std_logic_vector(2 downto 0 Elde_giris : I std_logic; Cikis : OUT std_logic_vector(15 downto 0 Tasma : OUT std_logic; Elde_cikis : OUT std_logic E D COMPO E T; COMPO E T gelistirilmis_kaydirici PORT( Kayan : I std_logic_vector(15 downto 0 Secici : I std_logic_vector(3 downto 0 Giren_Elde : I std_logic; Sonuc : OUT std_logic_vector(15 downto 0 Cikan_Elde : OUT std_logic E D COMPO E T; signal ALU_Cikis, Kay_Cikis,sonuc_ara: std_logic_vector(15 downto 0 20
Tek Vuruşluk Đşlemci signal C_art, C_man: std_logic; Inst_ALU: ALU PORT MAP( A_girisi => A_Girisi, B_girisi => B_Girisi, Secici => FS(3 downto 1), Elde_giris => FS(0), Cikis => ALU_Cikis, Tasma => V, Elde_cikis => C_art Inst_gelistirilmis_kaydirici: gelistirilmis_kaydirici PORT MAP( Kayan => B_Girisi, Secici => FS(3 downto 0), Giren_Elde => Elde_Girisi, Sonuc => Kay_Cikis, Cikan_Elde => C_man Sonuc_ara <= ALU_Cikis when FS(4)='0' else Kay_Cikis when FS(4)='1'; C <= C_art when FS(4)='0' else C_man when FS(4)='1'; <= sonuc_ara(15 Z <= '1' when sonuc_ara="0000000000000000" else '0'; Sonuc <= sonuc_ara; end Behavioral; 21
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : ALU -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity ALU is Port ( A_girisi : in STD_LOGIC_VECTOR (15 downto 0 B_girisi : in STD_LOGIC_VECTOR (15 downto 0 Secici : in STD_LOGIC_VECTOR (2 downto 0 Elde_giris : in STD_LOGIC; Cikis : out STD_LOGIC_VECTOR (15 downto 0 Tasma : out STD_LOGIC; Elde_cikis : out STD_LOGIC end ALU; architecture Behavioral of ALU is COMPO E T aritmetik_unitesi PORT( A_girisi : I std_logic_vector(15 downto 0 B_girisi : I std_logic_vector(15 downto 0 Elde_Girisi : I std_logic; Secici : I std_logic_vector(1 downto 0 Sonuc : OUT std_logic_vector(15 downto 0 Elde_Cikisi : OUT std_logic; Tasma_Cikisi : OUT std_logic E D COMPO E T; COMPO E T mantik_unitesi PORT( A_girisi : I std_logic_vector(15 downto 0 B_girisi : I std_logic_vector(15 downto 0 Secici : I std_logic_vector(1 downto 0 Cikis : OUT std_logic_vector(15 downto 0) E D COMPO E T; signal Aritmetik_sonuc, Mantiksal_sonuc: std_logic_vector(15 downto 0 Inst_aritmetik_unitesi: aritmetik_unitesi PORT MAP( 22
Tek Vuruşluk Đşlemci A_girisi => A_girisi, B_girisi => B_girisi, Elde_Girisi => Elde_giris, Secici => Secici(1 downto 0), Sonuc => Aritmetik_sonuc, Elde_Cikisi => Elde_Cikis, Tasma_Cikisi => Tasma Inst_mantik_unitesi: mantik_unitesi PORT MAP( A_girisi => A_girisi, B_girisi => B_girisi, Secici => Secici(1 downto 0), Cikis => Mantiksal_sonuc Cikis <= Aritmetik_sonuc when Secici(2)='0' else Mantiksal_sonuc when Secici(2)='1'; end Behavioral; 23
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : AU -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity aritmetik_unitesi is Port ( A_girisi : in STD_LOGIC_VECTOR (15 downto 0 B_girisi : in STD_LOGIC_VECTOR (15 downto 0 Elde_Girisi : in STD_LOGIC; Secici : in STD_LOGIC_VECTOR (1 downto 0 Sonuc : out STD_LOGIC_VECTOR (15 downto 0 Elde_Cikisi : out STD_LOGIC; Tasma_Cikisi : out STD_LOGIC end aritmetik_unitesi; architecture Behavioral of aritmetik_unitesi is COMPO E T full_adder PORT( a : I std_logic; b : I std_logic; c_in : I std_logic; s : OUT std_logic; c_out : OUT std_logic E D COMPO E T; type adder_bgirisi_ara_baglanti is array (0 to 15) of std_logic; signal B_girisi_to_adder,C_girisi_to_adder: adder_bgirisi_ara_baglanti; signal c_out_ara: std_logic; process(b_girisi,secici) for i in 0 to 15 loop B_girisi_to_adder(i)<=((B_girisi(i) and Secici(0)) or ((not B_girisi(i))and Secici(1)) end loop; end process; C_girisi_to_adder(0)<=Elde_Girisi; 24
Tek Vuruşluk Đşlemci Inst_full_adder0: full_adder PORT MAP( a => A_girisi(0), b => B_girisi_to_adder(0), c_in => C_girisi_to_adder(0), s => Sonuc(0), c_out => C_girisi_to_adder(1) Inst_full_adder1: full_adder PORT MAP( a => A_girisi(1), b => B_girisi_to_adder(1), c_in => C_girisi_to_adder(1), s => Sonuc(1), c_out => C_girisi_to_adder(2) Inst_full_adder2: full_adder PORT MAP( a => A_girisi(2), b => B_girisi_to_adder(2), c_in => C_girisi_to_adder(2), s => Sonuc(2), c_out => C_girisi_to_adder(3) Inst_full_adder3: full_adder PORT MAP( a => A_girisi(3), b => B_girisi_to_adder(3), c_in => C_girisi_to_adder(3), s => Sonuc(3), c_out => C_girisi_to_adder(4) Inst_full_adder4: full_adder PORT MAP( a => A_girisi(4), b => B_girisi_to_adder(4), c_in => C_girisi_to_adder(4), s => Sonuc(4), c_out => C_girisi_to_adder(5) Inst_full_adder5: full_adder PORT MAP( a => A_girisi(5), b => B_girisi_to_adder(5), c_in => C_girisi_to_adder(5), s => Sonuc(5), c_out => C_girisi_to_adder(6) Inst_full_adder6: full_adder PORT MAP( a => A_girisi(6), b => B_girisi_to_adder(6), 25
Kaynak Kodları c_in => C_girisi_to_adder(6), s => Sonuc(6), c_out => C_girisi_to_adder(7) Inst_full_adder7: full_adder PORT MAP( a => A_girisi(7), b => B_girisi_to_adder(7), c_in => C_girisi_to_adder(7), s => Sonuc(7), c_out => C_girisi_to_adder(8) Inst_full_adder8: full_adder PORT MAP( a => A_girisi(8), b => B_girisi_to_adder(8), c_in => C_girisi_to_adder(8), s => Sonuc(8), c_out => C_girisi_to_adder(9) Inst_full_adder9: full_adder PORT MAP( a => A_girisi(9), b => B_girisi_to_adder(9), c_in => C_girisi_to_adder(9), s => Sonuc(9), c_out => C_girisi_to_adder(10) Inst_full_adder10: full_adder PORT MAP( a => A_girisi(10), b => B_girisi_to_adder(10), c_in => C_girisi_to_adder(10), s => Sonuc(10), c_out => C_girisi_to_adder(11) Inst_full_adder11: full_adder PORT MAP( a => A_girisi(11), b => B_girisi_to_adder(11), c_in => C_girisi_to_adder(11), s => Sonuc(11), c_out => C_girisi_to_adder(12) Inst_full_adder12: full_adder PORT MAP( a => A_girisi(12), b => B_girisi_to_adder(12), c_in => C_girisi_to_adder(12), s => Sonuc(12), c_out => C_girisi_to_adder(13) 26
Tek Vuruşluk Đşlemci Inst_full_adder13: full_adder PORT MAP( a => A_girisi(13), b => B_girisi_to_adder(13), c_in => C_girisi_to_adder(13), s => Sonuc(13), c_out => C_girisi_to_adder(14) Inst_full_adder14: full_adder PORT MAP( a => A_girisi(14), b => B_girisi_to_adder(14), c_in => C_girisi_to_adder(14), s => Sonuc(14), c_out => C_girisi_to_adder(15) Inst_full_adder15: full_adder PORT MAP( a => A_girisi(15), b => B_girisi_to_adder(15), c_in => C_girisi_to_adder(15), s => Sonuc(15), c_out => c_out_ara Elde_Cikisi <= c_out_ara; Tasma_Cikisi <= C_girisi_to_adder(15) XOR c_out_ara; end Behavioral; -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Full Adder -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity full_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c_in : in STD_LOGIC; s : out STD_LOGIC; 27
Kaynak Kodları c_out : out STD_LOGIC end full_adder; architecture Behavioral of full_adder is --signal d: std_logic_vector(1 downto 0 s <= a XOR b XOR c_in; c_out <= (a A D b) OR (a A D c_in) OR (b A D c_in end Behavioral; 28
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : MU -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity mantik_unitesi is Port ( A_girisi : in STD_LOGIC_VECTOR (15 downto 0 B_girisi : in STD_LOGIC_VECTOR (15 downto 0 Secici : in STD_LOGIC_VECTOR (1 downto 0 Cikis : out STD_LOGIC_VECTOR (15 downto 0) end mantik_unitesi; architecture Behavioral of mantik_unitesi is Cikis <= (A_girisi and B_girisi) when Secici="00" else (A_girisi or B_girisi) when Secici="01" else (A_girisi xor B_girisi) when Secici="10" else not A_girisi when Secici="11"; end Behavioral; 29
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Gelistirilmis Kaydirici -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity gelistirilmis_kaydirici is Port ( Kayan : in STD_LOGIC_VECTOR (15 downto 0 Secici : in STD_LOGIC_VECTOR (3 downto 0 Giren_Elde : in STD_LOGIC; Sonuc : out STD_LOGIC_VECTOR (15 downto 0 Cikan_Elde : out STD_LOGIC end gelistirilmis_kaydirici; architecture Behavioral of gelistirilmis_kaydirici is COMPO E T temel_kaydirici PORT( kayan : I std_logic_vector(15 downto 0 sol_seri_giris : I std_logic; sag_seri_giris : I std_logic; secici : I std_logic_vector(1 downto 0 cikis : OUT std_logic_vector(15 downto 0) E D COMPO E T; COMPO E T mux PORT( giris : I std_logic_vector(3 downto 0 secici : I std_logic_vector(1 downto 0 cikis : OUT std_logic E D COMPO E T; signal sag_giris, sol_giris: std_logic; signal to_mux1, to_mux2: std_logic_vector(3 downto 0 to_mux1 <= Giren_elde & Kayan(0) & Kayan(15) & '0'; to_mux2 <= Giren_elde & Kayan(15) & "00"; Inst_temel_kaydirici: temel_kaydirici PORT MAP( kayan => Kayan, sol_seri_giris => sol_giris, 30
Tek Vuruşluk Đşlemci sag_seri_giris => sag_giris, secici => secici(3 downto 2), cikis => Sonuc Inst_mux1: mux PORT MAP( giris => to_mux1, secici => secici(1 downto 0), cikis => sol_giris Inst_mux2: mux PORT MAP( giris => to_mux2, secici => secici(1 downto 0), cikis => sag_giris Cikan_elde <= Kayan(0) when secici(3 downto 2)="01" else Kayan(15) when secici(3 downto 2)="10" else '0'; end Behavioral; 31
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Temel Kaydirici -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity temel_kaydirici is Port ( kayan : in STD_LOGIC_VECTOR (15 downto 0 sol_seri_giris : in STD_LOGIC; sag_seri_giris : in STD_LOGIC; secici : in STD_LOGIC_VECTOR (1 downto 0 cikis : out STD_LOGIC_VECTOR (15 downto 0) end temel_kaydirici; architecture Behavioral of temel_kaydirici is COMPO E T mux PORT( giris : I std_logic_vector(3 downto 0 secici : I std_logic_vector(1 downto 0 cikis : OUT std_logic E D COMPO E T; type mux_ara_baglanti is array (0 to 15) of std_logic_vector(3 downto 0 signal dis_to_mux: mux_ara_baglanti; process(kayan,sol_seri_giris,sag_seri_giris) for i in 1 to 14 loop dis_to_mux(i)<=('0' &kayan(i-1)&kayan(i+1)& kayan(i) end loop; dis_to_mux(0) <= ('0' & sag_seri_giris & kayan(1) & kayan(0) dis_to_mux(15) <= ('0' & kayan(14) & sol_seri_giris & kayan(15) end process; Inst_mux0: mux PORT MAP( giris => dis_to_mux(0), secici => secici, cikis => cikis(0) 32
Tek Vuruşluk Đşlemci Inst_mux1: mux PORT MAP( giris => dis_to_mux(1), secici => secici, cikis => cikis(1) Inst_mux2: mux PORT MAP( giris => dis_to_mux(2), secici => secici, cikis => cikis(2) Inst_mux3: mux PORT MAP( giris => dis_to_mux(3), secici => secici, cikis => cikis(3) Inst_mux4: mux PORT MAP( giris => dis_to_mux(4), secici => secici, cikis => cikis(4) Inst_mux5: mux PORT MAP( giris => dis_to_mux(5), secici => secici, cikis => cikis(5) Inst_mux6: mux PORT MAP( giris => dis_to_mux(6), secici => secici, cikis => cikis(6) Inst_mux7: mux PORT MAP( giris => dis_to_mux(7), secici => secici, cikis => cikis(7) Inst_mux8: mux PORT MAP( giris => dis_to_mux(8), secici => secici, cikis => cikis(8) Inst_mux9: mux PORT MAP( giris => dis_to_mux(9), secici => secici, cikis => cikis(9) 33
Kaynak Kodları end Behavioral; Inst_mux10: mux PORT MAP( giris => dis_to_mux(10), secici => secici, cikis => cikis(10) Inst_mux11: mux PORT MAP( giris => dis_to_mux(11), secici => secici, cikis => cikis(11) Inst_mux12: mux PORT MAP( giris => dis_to_mux(12), secici => secici, cikis => cikis(12) Inst_mux13: mux PORT MAP( giris => dis_to_mux(13), secici => secici, cikis => cikis(13) Inst_mux14: mux PORT MAP( giris => dis_to_mux(14), secici => secici, cikis => cikis(14) Inst_mux15: mux PORT MAP( giris => dis_to_mux(15), secici => secici, cikis => cikis(15) 34
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Çoklayici -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity mux is Port ( giris : in STD_LOGIC_VECTOR (3 downto 0 secici : in STD_LOGIC_VECTOR (1 downto 0 cikis : out STD_LOGIC end mux; architecture Behavioral of mux is cikis <= giris(conv_integer(secici) end Behavioral; -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Kontrol Unitesi -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; Library U ISIM; use U ISIM.vcomponents.all; entity kontrol_unitesi is port( v,c,n,z,clk,clr: in std_logic; mb,md,rw,mw : out std_logic; 35
Kaynak Kodları da,ba,aa : out std_logic_vector(3 downto 0 fs : out std_logic_vector(4 downto 0 end kontrol_unitesi; ci : out std_logic_vector(15 downto 0 counter : out std_logic_vector(14 downto 0) architecture Behavioral of kontrol_unitesi is component genisletici port( e0,e1 : in std_logic_vector(3 downto 0 extend: out std_logic_vector(14 downto 0) end component; component zero_fill port( zin : in std_logic_vector(3 downto 0 zout : out std_logic_vector(15 downto 0) end component; 0 component dallanma_kontrolu port( v,c,n,z,pl,jb : in std_logic; bc end component; branch_out : out std_logic : in std_logic_vector(2 downto component pc port( pc_in,clr,clk : in std_logic; extend : in std_logic_vector(14 downto 0 pc_out : out std_logic_vector(14 downto 0) end component; component komut_bellegi port( adress_in : in std_logic_vector(14 downto 0 data_out : out std_logic_vector(18 downto 0) end component; component komut_cozucu port( dr,sa,sb : in std_logic_vector(3 downto 0 opcode : in std_logic_vector(6 downto 0 mb,md,rw,mw,pl,jb : out std_logic; da,aa,ba : out std_logic_vector(3 downto 0 bc : out std_logic_vector(2 downto 0 fs : out std_logic_vector(4 downto 0) 36
Tek Vuruşluk Đşlemci end component; signal m_d : std_logic_vector(18 downto 0 signal p_l,j_b,bc_pc : std_logic; signal b_c : std_logic_vector(2 downto 0 signal extend,pc_m : std_logic_vector(14 downto 0 signal DO_in : std_logic_vector(31 downto 0 Modul1:genisletici port map( e0=>m_d(3 downto 0), e1=>m_d(11 downto 8), extend=>extend Modul2:zero_fill port map( zin=>m_d(3 downto 0), zout=>ci Modul3:dallanma_kontrolu port map( v=>v, c=>c, n=>n, z=>z, pl=>p_l, jb=>j_b, bc=>b_c, branch_out=>bc_pc Modul4:pc port map( pc_in=>bc_pc, clk=>clk, clr=>clr, extend=>extend, pc_out=>pc_m Modul5:komut_bellegi port map( adress_in=>pc_m, data_out=>m_d 37
Kaynak Kodları -- -- RAMB16_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4 Parity bits Single-Port RAM -- -- Xilinx HDL Language Template, version 9.2i -- -- RAMB16_S36_inst : RAMB16_S36 -- generic map ( -- I IT => X"000000000", -- Value of output RAM registers at startup -- SRVAL => X"000000000", -- Ouput value upon SSR assertion -- WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or O_CHA GE -- -- The following I IT_xx declarations specify the initial contents of the RAM -- -- Address 0 to 127 ---- 1111111100000000 11111111 00000000 11111111 00000000 11111111 00000000 -- I IT_00 => X"0004853F00005451000455430004243100002312000502050005010300000000",--7...0 -- I IT_01 => X"00063086000630230004C41F0000C61A0000E7400004A61F0000A64100008A12",--15..8 -- I IT_02 => X"0000000000067025000670850000000000000000000000000000000000000000",--23..16 -- I IT_04 => X"0001830500000000000000000000000000070004000000000000000000000000",--31..24 -- I IT_03 => X"0000000000000000000700000006000100000260000306500002002100014203",--39..32 -- I IT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 128 to 255 -- I IT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 256 to 383 -- I IT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", 38
Tek Vuruşluk Đşlemci -- I IT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 384 to 511 -- I IT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", -- I IT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- The next set of I ITP_xx are for the parity bits -- -- Address 0 to 127 -- I ITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I ITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 128 to 255 -- I ITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I ITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 256 to 383 -- I ITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I ITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", -- -- Address 384 to 511 -- I ITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", -- I ITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") -- port map ( -- DO => DO_in, -- 32-bit Data Output ---- DOP => DOP, -- 4-bit parity Output -- ADDR => pc_m(8 downto 0), -- 9-bit Address Input -- CLK => clk, -- Clock -- DI => "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", -- 32-bit Data Input -- DIP => "XXXX", -- 4-bit parity Input -- E => '1', -- RAM Enable Input -- SSR => clr, -- Synchronous Set/Reset Input -- WE => '0' -- Write Enable Input -- -- 39
Kaynak Kodları -- -- End of RAMB16_S36_inst instantiation -- --m_d <= DO_in(18 DOW TO 0 end Behavioral; Modul6:komut_cozucu port map( dr=>m_d(11 downto 8), sa=>m_d(7 downto 4), sb=>m_d(3 downto 0), opcode=>m_d(18 downto 12), mb=>mb, md=>md, rw=>rw, mw=>mw, pl=>p_l, jb=>j_b, da=>da, aa=>aa, ba=>ba, bc=>b_c, fs=>fs counter<=pc_m; 40
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Genisletici -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity genisletici is port( e0,e1 : in std_logic_vector(3 downto 0 extend: out std_logic_vector(14 downto 0) end genisletici; architecture Behavioral of genisletici is extend<= end Behavioral; "0000000" & e1 & e0 when e1(3)='0' else "1111111" & e1 & e0; 41
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Zero fill -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity zero_fill is port( zin : in std_logic_vector(3 downto 0 zout : out std_logic_vector(15 downto 0) end zero_fill; architecture Behavioral of zero_fill is end Behavioral; zout<="000000000000" & zin; 42
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Dallanma kontrolu -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity dallanma_kontrolu is port( v,c,n,z,pl,jb : in std_logic; bc : in std_logic_vector(2 downto 0 branch_out : out std_logic end dallanma_kontrolu; architecture Behavioral of dallanma_kontrolu is signal sec: std_logic; end Behavioral; with bc select sec <= c when "000", n when "001", v when "010", z when "011", (not c) when "100", (not n) when "101", (not v) when "110", (not z) when "111", '0' when others; branch_out <= pl and (sec or jb 43
Kaynak Kodları -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Program sayici -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity pc is port( pc_in,clk,clr: in std_logic; extend: in std_logic_vector(14 downto 0 pc_out: out std_logic_vector(14 downto 0) end pc; architecture Behavioral of pc is signal q: std_logic_vector(14 downto 0 end Behavioral; process(clr,clk,pc_in,extend,q) if(clr='1')then q<="000000000000000"; else if rising_edge(clk)then if(pc_in='1')then q<=q + extend; else q<=q + 1; end if; end if; pc_out<=q; end process; end if; 44
Tek Vuruşluk Đşlemci -- Company : Ege Universitesi, Elektrik-Elektronik Mühendisliği Bolumu -- Engineer : MOME TUM Proje Grubu -- Project ame : Tek Vurusluk Islemci -- Module ame : Komut bellegi -- Additional Comments : -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_U SIG ED.ALL; entity komut_bellegi is port( adress_in: in std_logic_vector(14 downto 0 data_out: out std_logic_vector(18 downto 0) end komut_bellegi; architecture Behavioral of komut_bellegi is with adress_in select data_out<= ---- "0000010011100010010" when "000000000000001", ---- ---- "0000010011100010010" when "000000000000010", ---- ---- "0000010000100010010" when "000000000000011", --1Movi Move data (immediate)- "1010000000100000011" when "000000000000001", --2Movi Move data (immediate) "1010000001000000101" when "000000000000010", --3Add Addition "0000010001100010010" when "000000000000011", --4Addi Addition (immediate) "1000010010000110001" when "000000000000100", --5Subi Subtraction (immediate) "1000101010101000011" when "000000000000101", --6Sub Subtraction "0000101010001010001" when "000000000000110", --7Andi A D (immediate) "1001000010100111111" when "000000000000111", --8And A D "0001000101000010010" when "000000000001000", --9Or OR "0001010011001000001" when "000000000001001",-- --10Ori OR (immediate) 45
Kaynak Kodları "1001010011000011111" when "000000000001010",-- --11 ot OT "0001110011101000000" when "000000000001011",-- --12Xor XOR "0001100011000011010" when "000000000001100",-- --13Xori XOR (immediate) "1001100010000011111" when "000000000001101",-- --14Beq Branch if equal to 0 "1100011000000100011" when "000000000001110",-- --15Beq Branch if equal to 0 "1100011000010000110" when "000000000001111",-- --16Bne Branch if not equal to 0 "1100111000010000101" when "000000000010101",-- --17Bne Branch if not equal to 0 "1100111000000100101" when "000000000010110",-- --18Ba Branch always "1110000000000000100" when "000000000011011",-- --19Sll Logical shift left "0011000001100000101" when "000000000011111",-- --20Srl Logical shift right "0010100001000000011" when "000000000100000",-- --21Sw Store word "0100000000000100001" when "000000000100001",---- --22Lw Load word "0110000011001010000" when "000000000100010",-- --23Mov Move data between registers "0000000001001100000" when "000000000100011",-- --24 op o operation "1100000000000000001" when "000000000100100",-- --25Hlt Halt "1110000000000000000" when "000000000100101", "1100000000000000000" when others; end Behavioral; 46