Ozet. Review pointers (in C) Memory Addressing

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1 Ozet Oku H&P Sections 31 thru 34 (read again) Section A10 Hardware-Software interface Processor nasil calisir Hardware ve software arasinda tradeoffs Show how processor works 11/26/2004 Bilgisayar Mimarisi 81 11/26/2004 Bilgisayar Mimarisi 82 Memory Addressing Her bir memory location 32 bit (4 byte) boyunda 4 byte data CPU ve memory arsinda transfer olur 32 bits of data transfer to and from memory simultaneously Memory byte addressable Sonraki memory location ina erismek icin onceki address e 4 eklenir Memory /26/2004 Bilgisayar Mimarisi Data Review pointers (in C) Pointer: an address stored in a variable int i = 17; // Primitive integer variable // contains a value int *p = &i; // pointer to an integer * means the variable is a pointer & means address of 11/26/2004 Bilgisayar Mimarisi 84

2 Pointer in Memory Integer data i is stored in location 1224 p points to the data is stored in location 1224 int value = *p; gives value 17 This accesses data indirectly Memory Pointer in Memory p++ adds 4 to p (p now 1228) (because we declared p as a pointer to an integer) Now p points to the data stored in location 1228 int value = *p; gives value Memory Data 32 Data 11/26/2004 Bilgisayar Mimarisi 85 11/26/2004 Bilgisayar Mimarisi 86 Memory Addressing Byte addr 000 Byte addr 003 MSB 32-bit word LSB Byte addr /26/2004 Bilgisayar Mimarisi 87 Memory Addressing Memory linear bir array, address 0 la baslar 4-byte align edilmis Leftmost byte daima 0, 4, 8, Address lerindedir Binary olarak, son iki bit haric butun address bitleri word u address ler, son iki bit ise word icindeki byte i address ler 11/26/2004 Bilgisayar Mimarisi 88

3 Memory addressing Bireysel byte lar address lenebilir, fakat word size 4 bytes 4 eklenerek bir sonraki word un address i bulunur 4 cikarilarak bir onceki word un address i bulunur 4 le carpilarak location numarasi address e donusturulur Memory addressing Decimal form da 4 uncu word un least significant byte (LSB) nin address i nedir? 11/26/2004 Bilgisayar Mimarisi 89 11/26/2004 Bilgisayar Mimarisi 810 Byte lari address leme 32-bit data path a sahip bir islemci nicin sadece word lari address lemez? 8-bit character ler cok yaygin Character lerin efficient bir sekilde memory de tutulmasi istenir Her bir character i word e yerlestirsek, memory gereksinimi 4 katina cikmis olacakti Memory address is a pointer Address bir yerde tutulmali Memory General purpose register PC Pointer buyulu bir sey degil Uzerinde islemler yapilabilen integer 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 812

4 MIPS memory addressing Load /store machine Memory den okuma sadece load instruction i ile olur Memory e yazma sadece store instruction i ile olur Byte, halfword, word icin load/store mumkun Double word pseudo instruction olarak gerceklenir General Register addressing 5 bit kullanilarak 32 register address lenir Ancak 32-bit word ler address lenir Bireysel byte lari address leme yok 5-bit address instruction code unda kodlanmistir 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 814 MIPS 32-bit word MIPS general registers MSB LSB We ll use this from now on, though I will occasionally slip back into familiar turf and number them 0 thru register a sahip Daha sonra bunlardan bahsedilecek simdilik temporary register lari kullanacagiz $t0 $t9 Gercek address leri 8 17 decimal 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 816

5 Source ve destination Assembler language program larda genel terimler Source: data nin geldigi yer Destination: sonucun gittigi yer add $t2, $t0, $t1 // R2 = R0 + R1 Sources: $t0 and $t1 (MIPS bunlari rs ve rt diye adlandirir) Destination: $t2 (MIPS bunu rd diye adlandirir) general register larin avantajlari Really hizli math ve logic operations! Register lar CPU chip inde Gunumuzde cok ucuz 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 818 general register larin dezavantajlari Data uzerinde islem yapmayan, ve sadece data nin tasinmasini saglayan load-store instruction larina ihtiyac var Complex programdaki tum variable lari tutacak sayida general register yok Subroutine ler cagrilirken register larin save edilmesi Code size uzar, daha kompleks, anlasilmasi daha zor 11/26/2004 Bilgisayar Mimarisi 819 Code this: F = (G + H) - (I + J) 3-operand memory machine ADD TEMPA, G, H ADD TEMPB, I, J SUB F, TEMPA,TEMPB MIPS is a 3-operand register machine 3-operand register machine LW $t0, G LW $t1, H ADD $t2, $t0, $t1 LW $t0, I LW $t1, J ADD $t3, $t0, $t1 SUB $t0, $t2, $t3 SW $t0, F 11/26/2004 Bilgisayar Mimarisi 820

6 MIPS instruction format R CPU Diagram, 3-operand assembler language op rs rt rd shamt funct Opcode reg addresses shift amount function Opcode IR R1 R2 Select R3 Ta ALU Tb PC MAR Address M U X MEM Opcode and function together specify the operation; don t know why MIPS splits them Rigid format -- wires come from their bits This is the Instruction Register -- next slide M U X General Registers Data 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 822 ADD $t2, $t0, $t1 which is R format SUB $t0, $t2, $t3 which is R format op rs rt rd shamt function op rs rt rd shamt function Only difference between ADD and SUB is one bit in the function field What does it control? remember next slide? 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 824

7 1-bit ALU for And, Or, Add, Sub InvertB A CarryIn Select Ain Bin MUX B Y MUX + Cin CarryOut 11/26/2004 Bilgisayar Mimarisi 825 design gereksinimleri load /store (word) instruction larina ihtiyac var Load/store memory i address lemek icin cok sayida bit e ihtiyac gosterir R format address adressleme icin yeterli alan yok IR 32 bit genisliginde Dolayisiyle yeni bir format tanimlanmali Instruction formati simple ve regular olmaktan uzaklasir (CISC mimarilerinin instruction formati ile karsilastirildiginda hala cok simple ve regular) 11/26/2004 Bilgisayar Mimarisi 826 MIPS instruction format I (immediate) LW $t1, 4($t0) which is I format I Format R Format op rs rt address op rs rt rd shamt funct op rs rt address I Format rt destination register destination register Loads, stores ve icinde immediate bulenan instruction formati 64K lik memory addresslenir (rs nin gosterdigi locationdan itibaren) 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 828

8 Immediate data Data instruction in icine konur addi $t0, $t1, 7 # t0 = t1 + 7 Small constant lari registerlarin iceriklerine eklemek icin yaygin bir yontem Immediate format kullanir ( I Format) Constant larin boyu 16 bitle sinirli (-32K thru 32K) I-Format ayni zamanda load/store icin kullanilir instruction format larin onemi Ezberlemeye gerek yok Sadece mantigi anlamaya calisilmali ve farkli amaclar icin nasil farkli yorumlandigi anlasilmali IR is rigid -- it is the hardware of the CPU See next slide 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 830 R I Multiple use of IR bits 5 To Gen Regs OP RS RT RD shamt funct OP RS RT address 16 To MAR Bits of opcode dictate which use 5 bits always go to two places, but only one J format Ucuncu format Jump instructionlari icin kullanilir 26-bit address leme yapar use is enabled subject of control 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 831

9 Instruction Jump Jump register Jump and link Jump and link register MAL jr R PC <-- R Jump Instructions j address PC<-address (address label veya register olabilir) jal address R 31 <-- PC + 4; PC <-- address jalr R d, R s R d <-- PC + 4; PC <--R s TAL j I ii iiii iiii iiii iiii iiii iiii PC <-- [PC] 3128 [I] jr R s ss sss PC <--[R s ] jal I R 31 <-- [PC] + 4; PC <-- [PC] 3128 [I] jalr R d, R s ss sss dddd d R d <-- [PC] + 4; PC <-- [R s ] 11/26/2004 Bilgisayar Mimarisi 833 Assembler directives Assemblerden sophistice seylerin yapilmasini istemek icin kullanilan command ler Genellikle memory allocation ile ilgili isler ile baslarlar Start with a pagea-51 11/26/2004 Bilgisayar Mimarisi 834 # Example to illustrate assembler directives # and general form of stand-along program align 2 # Align on full word boundary data # Allocate data here nsc: word 3 # Number of golf scores score: word 80, 82, 85 # Array of golf scores text # Program block starts here main: add $t4,$zero,$zero # Clear running sum in t4 la $t0, scores # t0 = base addr of scores 1208 is base addr of Scores Score 85 has an offset of 8 bytes (Java equivalent of Scores[2]) In MIPS, base addr is stored in a register offset is a constant la lw lw Base-offset addressing of integer arrays $t0, Scores # base addr to t0 $t1, 0($t0) # Scores[0] to t1 $t2, 8($t0) # Scores[2] to t Memory Scores 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 836

10 Instruction larin formatlari mimarinin performansina etkide bulunur Assembly dilleri memory e dogrudan erismeyi saglayan instructionlar icerirler Assembly dilinde data type kavrami yoktur Bellek gozlerindeki bitlerin sabit bir anlami yoktur Bu bitlerin anlami instructionlarin bunlari nasil kullandigina baglidir Bellekteki bir word unsigned integer, floating point number veya character (bir kac) olarak yorumlanabilir Hatta bu word bir instruction olarak da olabilir Instructions Bir cok modern processor lerin (MIPS RISC mimarisi dahil) instruction lari fixed-size (tum instructionlarin boyu ayni) 32-bit dir Instructionlarin fixed-size olmasi bir cok kolayliga yol acar Instruction larin fetch edilmesi (memory den CPU ya getirilmesi) Sonraki run olacak instruction in adresinin hesaplanmasi 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 838 Load/store architecture RISC Mimarisi Eger memory e sadece load/store instructionlariyle erisilebiliyorsa buna load/store architecture denir Modern RISC (Reduced Instruction Set Computer) processor ler load/store mimarisine sahiptirler Komutlarin kisa ve sabit uzunlukta olmasina yol acar 11/26/2004 Bilgisayar Mimarisi li yillarin sonu ve seksenli yillarin basinda RISC projesi yurutulmustur Proje IBM, Stanford University ve UC-Berkeley tarafindan ortaklasa yurutulmustur IBM 801, Stanford MIPS, Berkeley RISC 1, 2 Temel ozellikleri One cycle execution Pipelining Large number of registers 11/26/2004 Bilgisayar Mimarisi 840

11 MIPS RISC vs CISC 11/26/2004 Bilgisayar Mimarisi 841 MIPS mimarisi yaklasik 111 instructiondan olusur 21 arithmetic instructions (+, -, *, /, %) 8 logic instructions (&,, ~) 8 bit manipulation instructions 12 comparison instructions (>, <, =, >=, <=, ) 25 branch/jump instructions 15 load instructions 10 store instructions 8 move instructions 4 miscellaneous instructions 11/26/2004 Bilgisayar Mimarisi 842 Registers MIPS architecture iki farkli register file i vardir 32 genel register ($r0 $r31) Her biri 32-bit liktir 32 farkli registerin kodlanmasi icin 5 bit lik bir alan gerekir (instruction code) $r0 daima 0 (sifir) icerir $r1 assembler tarafindan kullanilir (makine diline translation sirasinda, pseudo instructions and large constants) $26 ve $27 operating system tarafindan kullanilirlar $28, $29 ve $r31 procedure cagriminda kullanilirlar (parameter passing, holding return address vs) Registers 32 floating point registers Floating point operand larini tutmak icin kullanilirlar $f0,, $f31 Floating point operands 32 (single precision)/64 (double precision) olabilir Double precision icin FP registerlar ciftler halinde kullanilabilirler ($f0,f1), ($f16, $f17) Odd numbered (tek numarali ) FP registerlar arithmetic instructionlarinda kullanilamazlar Sadece data transferleri icin kullanilabilirler 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 844

12 Registers Special purpose (ozel amacli) registers PC (Program Counter): Bir sonraki Execute edilecek instruction in adresini tutar SP (Stack Pointer) General purpose register file $r0 $r1 $r31 32 bit Floating point register file $f0 $f1 $f2 $f3 $f30 $f31 11/26/2004 Bilgisayar Mimarisi bit 11/26/2004 Bilgisayar Mimarisi 846 Load/Store Architecture Eger bellege erisim sadece load/store instructionlari ile sinirli ise buna load/store architecture denir Bu mimaride sadece iki grup instruction address belirlerler (load/store, control instructions) Veriler uzerinde islemler yapmak icin once bu veri bellekten okunup (load) bir register a yazilmasi gerekir Registerlar uzerinde islem yapildiktan sonra bellege tekrar yazilir (store) Butun RISC islemciler load/store architecture ina SAL: sub difference, subtrahend, minuend MAL: lw $8, subtrahend lw $9, minuend sub $10, $8, $9 sw $10, difference 11/26/2004 sahiptir Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 848

13 Instruction larda Adress Belirlenmesi Load/store architecture larda registerlar source (kaynak) operand lari temin eder (arithmetic ve logic instruction) Bu arithmetic ve logic instruction lari en fazla uc register kodlarlar (source1, source2, destination) Load/store instruction lari verinin bellekten okunacagi / yazilacagi adresi belirlemesi gerekir Brach instruction lari da branch edilecek instruction in adresini belirlemek zorunda SPIM de address ler 32 bit oldugu icin load/store veya branch instruction in kendisinde kodlanamazlar (instructionlarin uzunluklari 32 bit) 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 849 Effective Address Load/store ve branch instructionlari nasil address belirler? Effective address hesabi: load/store ve branch instruction larinin ifade ettigi address in hesaplanmasi Bunun icin cesitli yontemler var Addressing modes Islemciler cesitli methodlarla address belirlerler Bu yontemlere addressing modes denir Addressing modes operand in address inin nasil hesaplanmasi gerektigini belirler Immediate addressing Address direct olarak instructionin icine yerlestirilir Eger instruction da address icin 8 bitlik bir alan ayrilmissa bu alan olarak yorumlanabilir PC-relative Instruction Branch less than zero MAL bltz R, label If (R < 0), then PC<-- label TAL bltz R s, I ss sss iiii iiii iiii iiii if ([R s ] < 0), then PC <--[PC] +4 + ([I 15 ] 14 [I] ) 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 852

14 Register Operand bir register da bulunur Register Direct Operand in address i bir register da bulunur opcode reg one-word instruction opcode reg one-word instruction value reg address reg operand effective address 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 854 Base Displacement Effective address bir register in iceriginin (the base) instruction in icerisinde belirlenen bir constant (the displacement) a eklenmesiyle bulunur Bu mode indexed veya relative olarak da bilinir Instruction Load word MAL lw R, address R <-- M[address] TAL lw R t, I(R b ) bb bbbt tttt iiii iiii iiii iiii R t <-- M[[R b ] + (I 15 ) 16 I 15 0 ] opcode reg constant one-word instruction reg address 11/26/2004 Bilgisayar Mimarisi effective address /26/2004 Bilgisayar Mimarisi 856

15 Control Instructions Load/store mimarilerde sadece load/store instructions ve control instructions address belirlerler Kontrol instructions kosul dogru oldugunda gidilecek instruction in address ini belirlemek zorunda Genelde target address ler bulunulan yerden kisa mesafeler oldugu icin, cogu target address ler control instruction inin address ine kucuk degerli bir offset eklenerek bulunur (PC-relative label: beq var1, var2, label label program assembled edilirken hesaplanir beg var1,var2,offset addressing) 11/26/2004 Bilgisayar Mimarisi /26/2004 Bilgisayar Mimarisi 858 Load/Store Instructions Immediate addressing lw R, address En genel halde adreess bir constant, bir base register icerir Address, registerin belirledigi degere constant eklenmek suretiyle bulunur Address 4 un kati olmak zorunda lw $22, 12($25) displacement base register Target address: 12+[$12] 11/26/2004 Bilgisayar Mimarisi 859 li R, constant # R constant la R, label la $8, var_name lw $8, ($8) # label a bound olan variable addressini R ye yazar lw $8, var_name la $8, ar # load address of array ar add $8, $8, 20 # get address of sixth element lw $8, ($8) # load element ar[5] 11/26/2004 Bilgisayar Mimarisi 860

16 data ar: word 0:50 text # $8 -- a flag, 1 if the algorithm is done # $9 -- an offset to the correct element of the array # $10 -- address of the element to compare # $11 -- the array element for comparison # $12 -- the neighbor of the array element for comparison # $14 -- base address of array ar la $14, ar loop: li $8, 1 # flag = true li $9, 0 for: add $10, $14, $9 lw $11, ($10) # load element lw $12, 4($10) # load next element sub $13, $11, $12 blez $13, noswap # if they are in order, don t swap li $8, 0 sw $11, 4($10) # swap elements sw $12, ($10) noswap: add $9, $9, 4 sub $13, $9, 196 # see if end of the array reached blz $13, for beq $8, $0, loop # loop until done 11/26/2004 done Bilgisayar Mimarisi 861